In response to the need to miniaturize electronic products, multi-chip semiconductor package that encloses multiple chips in a single package has become a trend.
As disclosed in Chinese Patent Publication No. CN201063342Y, a multi-chip packaging structure includes: a first lead frame comprising a first chip carrier, a first internal pin and a second external pin; a second lead frame comprising a second chip carrier and a second internal pin; the second lead frame is positioned above or below the first lead frame, and the first lead frame is electrically connected to the second lead frame via a connector; the first chip is fixed on the first chip carrier, a bonding pad on the first chip is electrically connected to the first internal pin via a lead wire; the second chip is fixed on the second chip carrier, and a bonding pad on the second chip is electrically connected to the second internal pin via a lead wire; and a plastic molding that encapsulates the first chip carrier, the first internal pin, the first chip, the second lead frame and the second chip.
In existing technology, there is also such packaging structure as shown in FIG. 1, wherein the chip 2 is connected with the pin arrays 3 and 4 using the lead wire 1, then at the position indicated by the arrow in the figure, the pin arrays 3 and 4 may be cut into multiple arrays of pins 31, 32 and 41, 41, thus setting multiple pins for the semiconductor package for easy connection with the external circuit.
The above existing technology for chip packaging uses the lead wire for connection between the chip and the lead frame, but the multiple chips connected by the lead wire are usually apt to dislocated in the process of bonding and soldering re-flow, resulting in short circuit among lead wires and affecting the circuit performance.